1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor device packages and, more particularly, to a method for manufacturing dual chip packages (DCP) comprising two semiconductor chips.
2. Description of the Related Arts
Recently, semiconductor packaging technologies have been developed to satisfy demands for high density, increased capacity and miniaturization in the semiconductor industry. Particularly, multi-chip packages containing numerous semiconductor chips have been introduced and widely employed in assembly processes. One such approach is a stack package on which plural bare chips are three-dimensionally stacked in a single package.
FIG. 1 shows a conventional dual chip package 200 comprising two semiconductor chips, that is, a lower chip 110 and an upper chip 120. Herein, a lead frame on which the lower chip 110 is mounted, is referred to as a lower lead frame 130, and a lead frame on which the upper chip 120 is mounted, is referred to as an upper lead frame 140.
The lower chip 110 and the upper chip 120 are respectively mounted on and electrically wire-bonded to the lower lead frame 130 and the upper lead frame 140. The lower chip 110 and the upper chip 120 are center pad-type chips having electrode pads at the center of the active surface. The lower chip 110, the upper chip 120, the lower lead frame 130, the upper lead frame 140, and electrical connection portions including the bonding wire are all molded with a molding resin to form a package body 160.
Because the dual chip package 200 comprises two vertically stacked semiconductor chips 110, 120 and two vertically stacked lead frames 130, 140, its thickness is limited by the vertical dimension of these elements. It is especially difficult to manufacture a dual chip package having a thickness of about 1,000 mm.
Therefore, the overall thickness of the semiconductor chip and the lead frame needs to be minimized. However, extreme processing in the thickness of the semiconductor chip causes cracks in or damage to the semiconductor chip. Extreme processing in the thickness of the lead frame reduces the reliability of the wire bonding due to deformation of terminals of the inner leads. So, there are limits that the conventional DCP structure can achieve on reducing the thickness of the semiconductor chip and the lead frame.
Since lower bonding wires 156 and upper bonding wires 158 are respectively arranged over the lower surface of the lower lead frame 130 and the upper surface of the upper lead frame 140, the conventional DCP 200 has a drawback in that the lower bonding wires 156 and the upper bonding wires 158 easily extrude from the package body 160.
The inner leads 142 of the upper lead frame 140 and the inner leads 132 of the lower lead frame 130 are aligned and attached to each other by thermocompression method, and therefore attachment technique having high reliability is required. And, the lower bonding wires 156 extruding from the lower surface of the lower chip 110 are easily damaged during the manufacturing process.
Further, a step of removing the outer leads (not shown) from the lower lead frame 130 is further required.
Accordingly, an object of the present invention is to provide a method of manufacturing dual chip packages, which implements a thinner profile by mounting two chips on both sides of a single lead frame.
Another object of the present invention is to prevent package failures due to bonding wires.
In order to achieve the foregoing and other objects, the present invention provides a method of manufacturing a dual chip package using tape wiring boards.
According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are provided. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad. The upper chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the upper surface of the die pad. Each of the adhesive layers of the upper tape wiring board and the lower tape wiring board is attached to a respective one of the active surfaces of the upper chip and the lower chip. The windows of the lower and upper tape wiring boards expose the electrode pads of the lower and upper chips, respectively. Each of the pad connection portions is attached to a respective one of the electrode pads. Each of the lead connection portions is attached to a respective one of the inner leads. Next, the upper chip, the lower chip, the upper wiring board, and the lower wiring board are encapsulated to form a package body.